TR2021-034

InP Grating Coupler Design for Vertical Coupling of InP and Silicon Chips


    •  Tang, Y., Kojima, K., Gotoda, M., Nishikawa, S., Hayashi, S., Koike-Akino, T., Parsons, K., Meissner, T., Song, B., Sang, F., Yi, X., Klamkin, J., "InP Grating Coupler Design for Vertical Coupling of InP and Silicon Chips," Tech. Rep. TR2021-034, MERL Technical Report, May 2021.
      BibTeX TR2021-034 PDF
      • @techreport{Tang2021may,
      • author = {Tang, Yingheng and Kojima, Keisuke and Gotoda, Mitsunobu and Nishikawa, Satoshi and Hayashi, Shusaku and Koike-Akino, Toshiaki and Parsons, Kieran and Meissner, Thomas and Song, Bowen and Sang, Fengqiao and Yi, Xiongsheng and Klamkin, Jonathan},
      • title = {InP Grating Coupler Design for Vertical Coupling of InP and Silicon Chips},
      • institution = {MERL Technical Report},
      • year = 2021,
      • month = may,
      • url = {https://www.merl.com/publications/TR2021-034}
      • }
  • MERL Contacts:
  • Research Areas:

    Electronic and Photonic Devices, Machine Learning, Optimization, Signal Processing

Abstract:

We present the design and optimization strategy of shallow-angle grating couplers for vertical emission from InP devices.
When a long period (pitch: ~10 um) grating is written on an InGaAsP waveguide mounted on a Si substrate, downward emission at an angle of ~15 degrees inside the InP substrate occurs. This beam is reflected at the vertical cleaved facet, and the emission angle becomes ~55 degrees from the facet normal. With proper grating design, the near-circular beam can be focused on a Si grating coupler, and the coupling efficiency becomes larger than 50%, with 1 dB bandwidth of 35 nm, expected through simulation.
In this paper, we focus on the detailed grating design and the optimization strategy. Specifically, we use 2D finite difference time domain (FDTD) simulations and machine learning for the initial optimization. Sub-gratings are shown to decrease higher-order diffraction, resulting in higher coupling efficiency into a Si grating. We then use cascaded 3D FDTD simulations for the further optimization of the elliptic grating designs. The cascaded 3D simulations can give accurate result without using huge amount of resources.
Because the beam size can be as large as ~10 um, there is a possibility of passive alignment. Also, there is no need for special processing at the back side of the InP chip. Therefore, this work may pave the way for a new technology for low-cost InP-Si hybrid integration.